KirchhoffLM
A modern language model, Qwen3.5-0.8B, translated into an analog chip design: every weight is a pair of capacitors, every matrix product is done by currents adding up on wires (Kirchhoff's law), and the whole model runs through a physics emulator of 24 layer chips.
| Quality on emulated chips | +2.3 to +3.0 % bits/byte vs the original model (3 chips; 0.757–0.763 vs 0.740) |
| Long context | 20 / 20 recall of a fact hidden in ~981 tokens (exact model: 20 / 20) |
| Emulated speed | ~37,384 tokens/s for one user |
| Emulated energy | ~16 µJ per token at 2k context (estimate; most of it is the digital memory) |
| Hardware | 746,896,975 capacitors · 648,256 amplifiers · ~8,003 mm² over 25 chips |
| Weight cell | AC capacitor grid, up to 10 fF in 255 unit steps, 100 MHz carrier |
Start here
- Signal journey — follow one word through the chips, explained for a school student.
- Chip design — diagrams and every element of the chip.
- How it works and Assumptions — what the emulator models and what it does not.
- Results — quality, error budget, per-layer sensitivity, circuit checks.
- Alternative design — one programmable engine re-loaded layer by layer instead of one chip per layer.
A simulation study by UnaGo. No chip has been built; device values are literature-range assumptions and real silicon usually lands well below simulated efficiency. Related but different: KirchhoffNet (MIT/CMU, 2023) builds new continuous-time networks from circuits; KirchhoffLM maps an existing LLM onto realistic hardware and models its errors.