Status of these numbers

The device values are literature-range assumptions for a first exploration, not measurements of a specific fab process. Real silicon often lands 10–100× worse than simulation on energy because of control, clocking, leakage and interfaces that are not modelled.

Design parameters used by this chip

parameter	value	note
Largest cell capacitance	10 fF	metal-oxide-metal capacitor, ~2 fF/µm²
Carrier frequency	100 MHz	sets admittance ωC and read time
Drive amplitude	500 mV
Integration time per read	100 ns	≥ 3 carrier cycles
Tile size	128 cells	128 × 128 keeps wire phase delay small
Wire resistance per cell segment	2 Ω	dense crossbars: 1–5 Ω
Wire phase delay removed by calibration	0.9	per-column reference phase
Read-out amplifier power	3.54 µW	noise scales with 1/√P
Amplifier input noise at 10 µW	2 pA/√Hz
Amplifier gain mismatch	0.005
Offset left after synchronous detection	0.02	fraction of raw offset
Offset left after trimming (baseband circuits)	0.01	auto-zero
SiLU / sigmoid unit gain mismatch	0.01
Gilbert multiplier gain mismatch	0.01
Norm unit gain mismatch	0.005
Stray capacitance per crossing	50 aF	cancels in the pair except mismatch
Stray capacitance mismatch	0.1
ADC bits inside the chips	7 bits
Chip-to-chip link bits	10 bits
Rail = percentile of calibrated |signal|	100 %	100 = largest signal seen
Memory technology	sram	digital SRAM
Digital multiply-accumulate energy	200 fJ	incl. SRAM access
ADC energy per conversion step	5 fJ	Walden figure of merit

Capacitor cell

property	value
Unit capacitor	39.2 aF (255 per full cell)
Mismatch (Pelgrom)	σC/C = 0.4 % × √(1 fF / C): 0.13 % for a full 10 fF cell, 2.0 % for a single unit capacitor
Carrier phase noise	0.001 rad
Thermal noise in the grid	none (capacitors are noiseless; noise comes from the amplifiers)
Cell area	5.3 µm² per cell (two cells per weight)

Error sources and how each is modelled

effect	model	type
Capacitor mismatch	random per cell, Pelgrom's law σC = 0.4 % × √(1 fF × C): small capacitors have larger relative error	fixed per chip
Unit-capacitor rounding	weights rounded to 255 levels per row	fixed
Stray crossing capacitance	0.05 fF per crossing, 10 % mismatch between the pair	fixed per chip
Wire phase delay	distributed RC (Elmore) along row wires; detector keeps cos φ; 90 % calibrated	fixed
Amplifier noise	input current noise × √bandwidth, per read	random per read
Amplifier gain / offset	0.5 % gain; offset 0.2 % of range × 2 % left after demodulation	fixed per chip
Rails	inputs and outputs clip at the calibrated full scale	deterministic
SiLU / sigmoid / multipliers / norms	1 % gain, small trimmed offsets, tanh compression in multipliers	fixed per chip
ADCs and links	uniform rounding (checkpoint ADCs, 10-bit links, output ADC referenced to the peak)	deterministic
Memory converters	ADC into and DAC out of the digital memory: uniform rounding at 10 bits, per-head range for the DeltaNet read-out	deterministic
Digital memory	exact (SRAM, digital arithmetic)	—

Not modelled

• Leakage power of ~8,000 mm² of silicon, clock distribution, control logic, host I/O, cooling.
• Defects and redundancy repair; temperature gradients across a chip; supply noise; long-term ageing.
• Crosstalk between neighbouring wires along their full length is only partly modelled (it was included in the exact tile solves).
• The digital attention engine is assumed fast enough to keep up with ~1.1 µs per token per chip.