An alternative: one engine, re-programmed layer by layer
The main design keeps every weight fixed in place: one chip per layer. The alternative keeps the weights in memory and re-programs a small number of capacitor arrays for each layer. Each cell is a switched capacitor bank: 8 binary-weighted capacitors (1, 2, 4 … 128 unit capacitors) connected by switches that SRAM bits control, so a layer is loaded like memory. A sequencer broadcasts the layer index on a bus; while bank A computes layer i, bank B loads layer i+1.
Quality (Qwen3.5-0.8B, emulated)
| design | chip #0 | chip #1 | chip #2 |
|---|---|---|---|
| fixed capacitors, one chip per layer (current design) | +3.03 % | +2.36 % | +3.08 % |
| programmable bank, one array per layer | +3.09 % | +2.60 % | +3.27 % |
| programmable bank, one array per layer, program-and-verify | +3.19 % | +2.52 % | +3.23 % |
| programmable bank, shared array (multiplexed) | +4.62 % | +4.29 % | +4.57 % |
| programmable bank, shared array (multiplexed), program-and-verify | +4.67 % | +3.80 % | +4.63 % |
Programmable banks model every bit capacitor's Pelgrom error and the coupling of open switches. "Shared array" means all layers run on the same physical cells, so their manufacturing errors repeat in every layer. Program-and-verify uses the chip's measured errors to choose, for each weight, the switch code closest to the target.
Speed, energy, area: Qwen3.5-0.8B
| design | batch | tok/s per user | tok/s total | µJ per token | area mm² |
|---|---|---|---|---|---|
| one chip per layer (fixed) | — | 37,202 | 7,142,857 | 14.6 | 7,971 |
| multiplexed, on-chip SRAM | 1 | 3,876 | 3,876 | 97.2 (85 % reload) | 3,913 |
| multiplexed, on-chip SRAM | 128 | 2,205 | 282,187 | 15.3 (4 % reload) | 3,913 |
| multiplexed, on-chip SRAM | 1024 | 289 | 295,598 | 14.7 (1 % reload) | 3,913 |
| multiplexed, 3D-stacked SRAM | 1 | 7,752 | 7,752 | 1,294.3 (99 % reload) | 3,552 |
| multiplexed, 3D-stacked SRAM | 128 | 2,205 | 282,187 | 24.6 (41 % reload) | 3,552 |
| multiplexed, 3D-stacked SRAM | 1024 | 289 | 295,598 | 15.9 (8 % reload) | 3,552 |
| multiplexed, HBM | 1 | 1,938 | 1,938 | 33,079.9 (100 % reload) | 3,552 |
| multiplexed, HBM | 128 | 1,938 | 248,062 | 272.9 (95 % reload) | 3,552 |
| multiplexed, HBM | 1024 | 289 | 295,598 | 46.9 (69 % reload) | 3,552 |
| multiplexed, DDR | 1 | 194 | 194 | 123,895.9 (100 % reload) | 3,552 |
| multiplexed, DDR | 128 | 194 | 24,806 | 982.4 (99 % reload) | 3,552 |
| multiplexed, DDR | 1024 | 194 | 198,450 | 135.6 (89 % reload) | 3,552 |
Speed, energy, area: a 1T mixture-of-experts model (32B active)
| design | batch | tok/s per user | tok/s total | µJ per token | area mm² |
|---|---|---|---|---|---|
| one chip per layer (fixed) | — | 14,637 | 7,142,857 | 49.4 | 10,600,000 |
| multiplexed, on-chip SRAM | 1 | 62 | 62 | 5,169.4 (99 % reload) | 511,584 |
| multiplexed, on-chip SRAM | 128 | 62 | 8,000 | 89.4 (45 % reload) | 511,584 |
| multiplexed, on-chip SRAM | 1024 | 62 | 64,000 | 54.4 (9 % reload) | 511,584 |
| multiplexed, 3D-stacked SRAM | 1 | 125 | 125 | 79,409.4 (100 % reload) | 31,584 |
| multiplexed, 3D-stacked SRAM | 128 | 125 | 16,000 | 669.4 (93 % reload) | 31,584 |
| multiplexed, 3D-stacked SRAM | 1024 | 114 | 116,301 | 126.9 (61 % reload) | 31,584 |
| multiplexed, HBM | 1 | 31 | 31 | 2,050,609.4 (100 % reload) | 31,584 |
| multiplexed, HBM | 128 | 31 | 4,000 | 16,069.4 (100 % reload) | 31,584 |
| multiplexed, HBM | 1024 | 31 | 32,000 | 2,051.9 (98 % reload) | 31,584 |
| multiplexed, DDR | 1 | 3 | 3 | 7,682,609.4 (100 % reload) | 31,584 |
| multiplexed, DDR | 128 | 3 | 400 | 60,069.4 (100 % reload) | 31,584 |
| multiplexed, DDR | 1024 | 3 | 3,200 | 7,551.9 (99 % reload) | 31,584 |
What this shows
- Re-programming a layer takes about 10 µs, against about 1 µs of computing, so a load must serve many tokens (many users, or a long prompt). Single-user speed drops about 10×.
- With weights in on-chip SRAM and batches of 128 or more, the energy per token matches the fixed design with about half the silicon.
- With weights in off-chip memory (HBM, DDR) moving the weights costs most of the energy again: the memory wall that analog compute was meant to avoid. A 3D-stacked weight store on top of the engine keeps that cost low and is the only route that scales to 1T.
- Per-user memory (DeltaNet state, KV cache) must also be swapped per layer, so batch size is limited by memory, as on GPUs.
- Quality: programmable banks cost almost nothing compared with fixed capacitors. Sharing one physical array across all layers costs about 1.5 points, and that comes from per-column errors (amplifier gain and offset, wire phase, stray capacitance) repeating in every layer, not from the capacitor cells, so program-and-verify of the cells does not remove it. Per-column amplifier trims would be the next step.
Timing and energy come from an order-of-magnitude model (emulator/multiplex_model.py), not from the circuit emulator. For a mixture-of-experts model, tokens in one batch use different experts, so the reuse per load is lower than assumed here.