What you are talking to
The chat model is Qwen3.5-0.8B, translated into a hardware design: every weight became a pair of capacitors (counted in unit capacitors), every read-out amplifier got a feedback-resistor value, every norm a set of gain resistors. The website loads only that design package — 746,896,975 capacitors made of 30,616,073,459 unit capacitors, 648,256 amplifiers — and runs it through an emulator of the chips.
What the emulator does for every token
- Weight grids. The input vector becomes sine-wave voltages on the rows of each capacitor grid. The column currents add up by Kirchhoff's law, which is the matrix–vector product. The emulator computes the same sum, then applies the physics: capacitor mismatch, stray capacitance, wire phase delay (after calibration), amplifier gain/offset error and noise, and clipping at the rails.
- Analog circuits. Norm units, SiLU/sigmoid transistor stages and Gilbert-cell multipliers get their own mismatch, offsets and limits.
- Digital parts. The memory of earlier tokens (DeltaNet state, attention KV cache) is digital SRAM; ADCs and DACs at its boundary round the values. Chips talk through 10-bit digital links.
- Incremental operation. Like the real chips, each layer chip keeps its state between tokens; every new token makes one pass through the 24 chips.
- Manufacturing. The "chip number" selects one random draw of the fixed manufacturing errors — different numbers are different physical chips with the same design.
Two kinds of time
The processing log shows both. Emulator time is how long the Mac takes to simulate the physics (~30 tokens/s). Emulated hardware time is how long the real chips would take according to the circuit timing model (~37,000 tokens/s, ~1.1 µs per chip per token). The emulator is slower than the hardware it emulates.
How the emulator was checked
- With all physics off it reproduces the digital model exactly (logit difference ~5×10⁻⁵).
- Incremental mode equals full recompute (exactly with physics off, statistically with physics on).
- The fast weight-grid model was checked against an exact circuit solve of real 128×128 tiles (every wire segment, cell and stray capacitor as a node, solved like SPICE for linear circuits) — the AC design agrees within ~0.3 % per tile.