Qwen3.5-0.8B: quality on the emulated chips

run	bits/byte	vs original
Original digital model	0.7403	—
Design package values only (no physics)	0.7398	-0.06 %
Emulated chip #0	0.7623	+2.97 %
Emulated chip #1	0.7573	+2.29 %
Emulated chip #2	0.7626	+3.01 %

12 held-out texts (6 Wikipedia, 6 code), 1,024 tokens each; 10-bit chip links; lower bits/byte is better.

Long context (1,024 tokens)

test	exact model	emulated chip
Recall a number hidden early in ~981 tokens (20 trials)	20 / 20	20 / 20
Bits/byte, tokens 0–256	0.8250	0.8514 (+3.2 %)
Bits/byte, tokens 256–512	0.7932	0.8182 (+3.1 %)
Bits/byte, tokens 512–768	0.6867	0.7075 (+3.0 %)
Bits/byte, tokens 768–1023	0.6748	0.6994 (+3.6 %)

The hardware error does not grow with context, because the memory of earlier tokens is digital.

Error budget

Sensitivity per layer

Exact circuit solves of one real tile (layer 0 FFN)

design	tile	wire R	line coupling	output error (after calibration)
DC resistor 73uS, 0.09 V	128	0.5 Ω	0 fF	15.24 %
DC resistor 73uS, 0.09 V	128	2 Ω	0 fF	39.93 %
DC resistor 73uS, 0.09 V	128	4 Ω	0 fF	57.55 %
AC cap 10fF @100MHz, 0.5 V	128	0.5 Ω	0 fF	0.17 %
AC cap 10fF @100MHz, 0.5 V	128	2 Ω	0 fF	0.21 %
AC cap 10fF @100MHz, 0.5 V	128	4 Ω	0 fF	0.54 %
AC cap 2fF @1GHz, 0.5 V	128	0.5 Ω	0 fF	0.83 %
AC cap 2fF @1GHz, 0.5 V	128	2 Ω	0 fF	1.05 %
AC cap 2fF @1GHz, 0.5 V	128	4 Ω	0 fF	2.61 %
DC resistor 73uS, 0.09 V	256	0.5 Ω	0 fF	40.04 %
DC resistor 73uS, 0.09 V	256	2 Ω	0 fF	73.58 %
DC resistor 73uS, 0.09 V	256	4 Ω	0 fF	86.13 %
AC cap 10fF @100MHz, 0.5 V	256	0.5 Ω	0 fF	0.22 %
AC cap 10fF @100MHz, 0.5 V	256	2 Ω	0 fF	1.95 %
AC cap 10fF @100MHz, 0.5 V	256	4 Ω	0 fF	6.88 %
AC cap 2fF @1GHz, 0.5 V	256	0.5 Ω	0 fF	1.08 %
AC cap 2fF @1GHz, 0.5 V	256	2 Ω	0 fF	8.61 %
AC cap 2fF @1GHz, 0.5 V	256	4 Ω	0 fF	24.03 %

DC resistor grids distort badly through wire voltage drop unless every cell is pre-compensated; the AC capacitor grid at 10 fF / 100 MHz stays within a fraction of a percent.

Small model trained digitally, run on the chip (TinyStories, 5.8M weights)

	validation loss
Exact	2.2000
Emulated chip #0	2.2036
Unseen chips #1–4	2.2043, 2.2038, 2.2040, 2.2037

Speed and energy (estimates)

	emulated analog chain	M3 Max GPU (measured, digital)	H100 (estimated)
Generation, one user	~37,384 tokens/s	191 tokens/s	~800–1,600 tokens/s
Energy per token, one user	~16 µJ at 2k context	~0.2 J	~0.3 J
1,024-token prompt	1.2 ms, 8.9 mJ	134 ms	~3–6 ms, ~2–4 J

Corrections

2026-10-16: an external review found four issues. (1) The converters around the digital memory were not simulated; (2) capacitor mismatch did not grow for small capacitors as Pelgrom's law requires; (3) the design search crashed for capacitor grids; (4) the numerical checks did not assert. Fixing them also exposed (5) a calibration that took the signal peak from a random subsample, so rails clipped real peaks, and (6) a memory ADC with one range for all channels, which rounded quiet heads away. All are fixed, covered by regression tests, and every number on this site was re-measured afterwards. The design now uses per-head ADC ranges (10 bits) into the memory and 12-bit DACs out of it.

Analog numbers come from the circuit timing and energy model of an unbuilt chip; NVIDIA numbers are scaled from the M3 Max measurement using memory bandwidth and compute specs. Treat all of them as order-of-magnitude.